A symmetric multiprocessing (SMP) architecture generally is a multiprocessor computer architecture where two or more identical processors can connect to a single shared main memory. In the case of multi-core processors, the SMP architecture can apply to the CPU cores.
In an SMP architecture, multiple networking CPUs or CPU cores can receive and transmit network traffic. Typically, an atomic global counter is usually used across the multiple networking CPUs and/or networking CPU cores. This may slow down the performance of multiple processors or CPU cores. When the networking CPUs and/or CPU cores perform network packet processing, a large number of increments and decrements are performed on multiple counters by the multiple networking CPUs and/or CPU cores when the packets are received and transmitted or forwarded.
Moreover, it is possible that multiple CPUs try to access the same data structure in memory at the same time. This may cause certain indeterministic behaviors, including, for example, incorrect reading of data values, etc. Therefore, both the existing locking mechanism on the shared memory and the ability for multiple networking CPU cores to gain write access to the shared memory may degrade the performance of multiple networking CPUs and/or networking CPU cores in the SMP architecture.
In some scenarios, a network packet may be divided into multiple fragments. Each fragment may be received by the same or different network CPU or CPU cores. Because not all fragments include the necessary header information for packet processing, special handlings of such fragmented packets are needed by the network CPU or CPU cores.